Static Random Access Memory (SRAM) is a critical component in most integrated circuit designs. A typical 6-transistor SRAM cell 100 circuit schematic is shown in FIG. 1. It is based on a pair of cross-connected inverters, and includes a first inverter made with a first P-channel pull-up transistor PU1 110 and a first N-channel pull-down transistor PD1 112, and a second inverter made with a second P-channel pull-up transistor PU2 114 and a second N-channel pull-down transistor PD2 116. The drain of transistor PU1 is connected to the drain of transistor PD1, and the drain of transistor PU2 is connected to the drain of transistor PD2. The sources of both transistors PU1 and PU2 are connected to a power source line Vdd 118 and the sources of both transistors PD1 and PD2 are connected to a reference line Vss 120. The gates of transistors PU1 and PD1 are connected together and to the node connecting the drain of PU2 with the drain of PD2. Similarly, the gates of transistors PU2 and PD2 are connected together and to the node connecting the drain of PU1 with the drain of PD1. The ‘true’ bit line BL is connected to the gates of transistors PU2 and PD2 through a first pass-gate transistor PG1, and the ‘complement’ bit line BLB is connected to the gates of transistors PU1 and PD1 through a second pass gate transistor PG2. As used herein, the terms “true” and “complement” bit lines are used as a convenience to mean opposite polarity bit lines of a differential pair. In a particular array, which bit line is considered “true” and which is considered “complement” depends on circuitry outside the array.
A typical write operation for the SRAM cell of FIG. 1 includes applying the value to be written to one of the bit lines and its complement to the other. The word line is then asserted and the bit line values override any value previously stored in the cell, and the cross-coupled inverters lock in the new value. The word line is then de-asserted.
A typical FinFET-based layout of the 6-transistor cell 100 is shown in FIG. 2. The layout diagram shows an N-channel diffusion 210, in which channel regions of transistors PG1 and PD1 are defined by gate electrodes 212 and 214, respectively. A gate electrode 214 defines the channel region of transistor PU1 in a P-channel diffusion 216. The gates electrodes 220 and 222 define the channel regions of transistors PD2 and PG2 in the N-channel diffusion 218 respectively. The gate electrode 220 defines the channel region of transistor PU2 in the P-channel diffusion 224. The diffusions 210, 216, 218 and 224 are formed in fins. A local metal interconnect 226 connects the gate electrode 220 to the junction between transistors PG1, PD1, and PU1, and a local interconnect 228 connects the gate electrode 214 to the junction between transistors PG2, PD2, and PU2. Higher level metal interconnects are not shown in FIG. 2, but connections to WL, BL, BLB, Vdd, and Vss are indicated. In general, unless otherwise stated, for clarity of illustration, such higher level interconnects are not shown in any of the layout drawings herein. As used herein, a “fin” is a segment of semiconductor ridge material which is physically spaced by dielectric materials (including air) from all other segments of semiconductor ridge material.
In general, “hot carriers” are particles that attain a very high kinetic energy from being accelerated by a high electric field in P-channel and N-channel transistors. These energetic carriers can be injected into normally forbidden regions of the device, such as the gate dielectrics of the transistors, where they can get trapped. These defects can then lead to threshold voltage shifts in the transistors and can be a major reliability concern in the performance of an SRAM cell.
With the introduction of high-k gate dielectrics in P-channel and N-channel transistors, bias temperature instability (BTI) is also another major reliability concern in SRAM cells. BTI happens when the gate of a heated transistor is heavily or nominally biased while keeping the source and drain grounded for n-channel transistors or when the gate of a heated transistor is grounded or negatively biased while keeping the source and drain at Vdd level. BTI may also happen in an analog circuit when the drain-source bias is non zero. Under these conditions, charges can get trapped in the gate dielectrics of the p-channel and n-channel transistors and degrade the threshold voltage of the transistors. A prominent form occurs when the gate of a p-channel transistor is biased negatively (in the strong inversion regime). This effect is known as the negative bias temperature instability (NBTI). When the gate is biased positively for N-channel devices, the phenomenon is called positive bias temperature instability (PBTI). As a consequence of BTI, the overall change of the threshold voltages of the transistors can increase the probability that the transistors fail to operate properly, which may yield a malfunctioning transistor (though not necessarily destroyed yet).
Aspects of the invention address the problem of trapped charges in gate dielectrics of P-channel pull-up transistors and N-channel pull-down transistors in an SRAM cell.